Consortium for Development of Vertically Integrated (3D) Readout Electronics and Sensors

Vertical integration or 3D for short is defined as “the integration of thinned and bonded silicon integrated circuits with vertical interconnects between IC layers”1. The definition might be best understood by means of an example as seen in the schematic below which show a three tier IC stack comprised of two layers of electronics and one sensor layer. This device was fabricated by MIT Lincoln labs. The active electronics in each layer is only 7 microns thick. A CAD layout view of one pixel element is also shown for clarity showing the vertical interconnects.

The 3D technology is being explored by industry for many applications including memories, pixel arrays, microprocessors, and FPGAs. This consortium has been form to explore vertical integration for pixel arrays in a number of scientific applications. 3D offers the opportunity to develop low mass circuits with high circuit density along with isolation of various elements such as analog and digital circuits.

1 Handbook of 3D Integration, edited by Philip Garrou, Christopher Bower, and Peter Ramm, Wiley-VCH, 2008